1. Field of the Invention
The present invention relates to a microcomputer having memory interface circuits and a semiconductor device such as an SIP (system in package) having a microcomputer and memories on a module board. For example, the invention relates to a technique which is effectively applied to a microcomputer having memory interface circuits connectable with DDR (double data rate) 2-SDRAM (synchronous dynamic random access memory) in conformity to JEDEC STANDARD No. 79-2B.
2. Description of the Related Art
There is JEDEC STANDARD as international standards for SDRAM, which standardizes pin arrangements, pin functions, operation modes, and other specifications. For example, according to DDR2-SDRAM specified in JEDEC STANDARD No. 79-2B shown in JEDEC STANDARD, DDR2 SDRAM SPECIFICATION JESD 79-2B (Revision of JESD 79-2A), January 2005, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, data strobe signals and clock signals are differential pairs, and data and data strobe signal pin arrays are separated from command and address pin arrays. Particularly in the interface specification having the parallel data input/output bit number of 16 bits (×16 bits), the data and data strobe signal pin arrays having upper bytes are further separated from the data and data strobe signal pin arrays having lower bytes.
The inventors of the invention have examined a memory interface circuit corresponding to DDR2-SDRAM in a microcomputer containing a memory controller. With current development in the fields of operation voltage reduction, circuit element miniaturization and others, decrease in the sizes of chip and package in a microcomputer has been promoted. When the chip is made compact, the number of input/output circuit cells (I/O cells) which can be arranged around the chip is limited. For example, data and data strobe interface of a DDR2-SDRAM for data of one byte further requires a corresponding differential pair and a data mask signal of 3 bits, that is, I/O cells of 11 bits in total. When the cell width of one I/O cell is approximately 80 μm, a width of at least 880 μm is necessary for only the interface signal of one byte. When the width is almost doubled considering that power supply and GND cells are contained, 1760 μm is required. Thus, 7040 μm is needed for the interface signal of four bytes, and a width of 7 mm or larger is necessary for only the data and data strobe interface. Therefore, the data and data strobe interface cannot be disposed on one side of a square chip having 7 mm or smaller for one side. It is also considered that a rectangular chip having longer sides of 7 mm or larger is used. In this case, however, the correlation between the circuit positions and the circuit characteristics becomes closer on the chip, and the possibility of deterioration in the reliability increases. The inventors of the invention investigated the positions of the memory interface pin arrays which realize miniaturization of the microcomputer chip and package. Moreover, the inventors clarified the necessities for improvements from other viewpoints required for this miniaturization as well as the arrangement of the memory interface pin arrays when a plurality of bare chips or the like are mounted on a module board with high density. The “other viewpoints” herein include noise resistance, external attachment positions of electronic components, testability of plural sealed chips, and others which are important for high-density line arrangement.